Sciweavers

135 search results - page 13 / 27
» Code and Data Transformations for Improving Shared Cache Per...
Sort
View
ASPLOS
1994
ACM
13 years 11 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
13 years 5 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...
CGO
2004
IEEE
13 years 11 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
PDP
2010
IEEE
14 years 2 months ago
Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems
—This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a seve...
Juan Angel Lorenzo, Juan Carlos Pichel, David LaFr...
EUROSYS
2011
ACM
12 years 11 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang