135 search results - page 21 / 27 » Code and Data Transformations for Improving Shared Cache Per... |
134
Voted
HPCA
1995
IEEE
15 years 7 months ago
1995
IEEE
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
146
Voted
SIGARCH
2008
15 years 3 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
104
Voted
MICRO
2000
IEEE
15 years 8 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
153
Voted
HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
153
Voted
EMSOFT
2005
Springer
15 years 9 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...