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ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
14 years 1 months ago
Learning-Based SMT Processor Resource Distribution via Hill-Climbing
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
Seungryul Choi, Donald Yeung
CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
IPPS
2007
IEEE
14 years 1 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...
CASES
2008
ACM
13 years 9 months ago
Efficient code caching to improve performance and energy consumption for java applications
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
Yu Sun, Wei Zhang
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
13 years 11 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...