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» Code generation for fixed-point DSPs
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DATE
2002
IEEE
161views Hardware» more  DATE 2002»
13 years 12 months ago
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
Heiko Michel, Alexander Worm, Norbert Wehn, Michae...
IEEEPACT
2000
IEEE
13 years 11 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
13 years 11 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
13 years 10 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
ICESS
2007
Springer
14 years 1 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam