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    » Collaborative Routing Architecture for FPGA
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    FPGA
    2006
    ACM
    125views FPGA» more  FPGA 2006»
    Armada: timing-driven pipeline-aware routing for FPGAs
    13 years 11 months ago
    Armada: timing-driven pipeline-aware routing for FPGAs
    Download  www.ee.washington.edu
    While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
    Kenneth Eguro, Scott Hauck
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    DAC
    1995
    ACM
    130views Computer Architecture» more  DAC 1995»
    Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
    13 years 11 months ago
    Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
    Download  www.cecs.uci.edu
    We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
    Yu-Liang Wu, Malgorzata Marek-Sadowska
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    VLSISP
    2002
    199views more  VLSISP 2002»
    Evaluation of CORDIC Algorithms for FPGA Design
    13 years 7 months ago
    Evaluation of CORDIC Algorithms for FPGA Design
    Download  bwrc.eecs.berkeley.edu
    Abstract. This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the...
    Javier Valls, Martin Kuhlmann, Keshab K. Parhi
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    FPGA
    1999
    ACM
    115views FPGA» more  FPGA 1999»
    Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
    13 years 11 months ago
    Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
    Download  www.eecg.toronto.edu
    In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
    Alexander Marquardt, Vaughn Betz, Jonathan Rose
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    DT
    1998
    85views more  DT 1998»
    How Much Logic Should Go in an FPGA Logic Block?
    13 years 7 months ago
    How Much Logic Should Go in an FPGA Logic Block?
    Download  www.eecg.toronto.edu
    The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related ...
    Vaughn Betz, Jonathan Rose
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