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FPL
2005
Springer
98views Hardware» more  FPL 2005»
14 years 1 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose
APCSAC
2001
IEEE
13 years 11 months ago
The First Real Operating System for Reconfigurable Computers
Traditional reconfigurable computing platforms are designed to be single user and have been acknowledged to be difficult to design applications for. The design tools are still pri...
Grant B. Wigley, David A. Kearney
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
13 years 11 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 11 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
TVLSI
2008
111views more  TVLSI 2008»
13 years 7 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...