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DATE
2007
IEEE
185views Hardware» more  DATE 2007»
14 years 2 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha
CDES
2008
90views Hardware» more  CDES 2008»
13 years 9 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
HPCC
2010
Springer
13 years 6 months ago
Implementation and Evaluation of a NAT-Gateway for the General Internet Signaling Transport Protocol
The IETF's Next Steps in Signaling (NSIS) framework provides an up-to-date signaling protocol suite that can be used to dynamically install, maintain, and manipulate state in ...
Roland Bless, Martin Röhricht
CGO
2008
IEEE
14 years 2 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
HPCC
2009
Springer
14 years 17 days ago
C2Cfs: A Collective Caching Architecture for Distributed File Access
—In this paper we present C2Cfs - a decentralized collective caching architecture for distributed filesystems. C2Cfs diverges from the traditional client-server model and advoca...
Andrey Ermolinskiy, Renu Tewari