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IJNSEC
2008
106views more  IJNSEC 2008»
13 years 8 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
JSAC
2006
172views more  JSAC 2006»
13 years 8 months ago
A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection
The ability to inspect both packet headers and payloads to identify attack signatures makes network intrusion detection system (NIDS) a promising approach to protect Internet syste...
Hongbin Lu, Kai Zheng, Bin Liu, Xin Zhang, Y. Liu
JSA
2007
123views more  JSA 2007»
13 years 8 months ago
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
CN
2011
139views more  CN 2011»
13 years 3 months ago
MultiCache: An overlay architecture for information-centric networking
—It has become apparent for quite some time that the Internet has evolved from a network connecting pairs of end-hosts to a substrate for information dissemination. While this sh...
Konstantinos V. Katsaros, George Xylomenos, George...
ASAP
2009
IEEE
143views Hardware» more  ASAP 2009»
14 years 5 months ago
Scalar Processing Overhead on SIMD-Only Architectures
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...
Arnaldo Azevedo Filho, Ben H. H. Juurlink