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» Collaborative architecture design and evaluation
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CODES
2004
IEEE
14 years 2 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
TC
2010
13 years 8 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
HPCA
2007
IEEE
14 years 10 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed
MOBISYS
2004
ACM
14 years 9 months ago
Bluetooth and WAP Push Based Location-Aware Mobile Advertising System
Advertising on mobile devices has large potential due to the very personal and intimate nature of the devices and high targeting possibilities. We introduce a novel B-MAD system f...
Lauri Aalto, Nicklas Göthlin, Jani Korhonen, ...
IVA
2009
Springer
14 years 4 months ago
Varying Personality in Spoken Dialogue with a Virtual Human
We extend a virtual human architecture that has been used to build tactical questioning characters with a parameterizable personality model, allowing characters to be designed with...
Michael Rushforth, Sudeep Gandhe, Ron Artstein, An...