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SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 3 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
IPSN
2004
Springer
14 years 3 months ago
Flexible power scheduling for sensor networks
We propose a distributed on-demand power-management protocol for collecting data in sensor networks. The protocol aims to reduce power consumption while supporting fluctuating dem...
Barbara Hohlt, Lance Doherty, Eric A. Brewer
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
14 years 2 months ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
DAC
2010
ACM
14 years 2 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
GLOBECOM
2009
IEEE
14 years 1 months ago
Inter-Gateway Cross-Layer Handoffs in Wireless Mesh Networks
—Wireless mesh networks (WMNs) have recently emerged to be a cost-effective solution to support large-scale wireless Internet access. One important component of realizing large-s...
Weiyi Zhao, Jiang Xie