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ITNG
2008
IEEE
14 years 3 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
ICPPW
2000
IEEE
14 years 1 months ago
Flits: Pervasive Computing for Processor and Memory Constrained Systems
Many pervasive computing software technologies are targeted for 32-bit desktop platforms. However, there are innumerable 8, 16, and 32-bit microcontroller and microprocessor-based...
William Majurski, Alden Dima, Mary Laamanen
DAC
2005
ACM
13 years 11 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
VR
2002
IEEE
117views Virtual Reality» more  VR 2002»
14 years 1 months ago
DLoVe: Using Constraints to Allow Parallel Processing in Multi-User Virtual Reality
In this paper, we introduce DLoVe, a new paradigm for designing and implementing distributed and nondistributed virtual reality applications, using one-way constraints. DLoVe allo...
Leonidas Deligiannidis, Robert J. K. Jacob
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 11 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III