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» Collection and Analysis of Microprocessor Design Errors
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ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
14 years 23 days ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
BMCBI
2008
204views more  BMCBI 2008»
13 years 7 months ago
EST2uni: an open, parallel tool for automated EST analysis and database creation, with a data mining web interface and microarra
Background: Expressed sequence tag (EST) collections are composed of a high number of single-pass, redundant, partial sequences, which need to be processed, clustered, and annotat...
Javier Forment, Francisco Gilabert Villamón...
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 1 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
DAS
2006
Springer
13 years 11 months ago
A Semi-automatic Adaptive OCR for Digital Libraries
This paper presents a novel approach for designing a semi-automatic adaptive OCR for large document image collections in digital libraries. We describe an interactive system for co...
Sachin Rawat, K. S. Sesh Kumar, Million Meshesha, ...
GLVLSI
2003
IEEE
186views VLSI» more  GLVLSI 2003»
14 years 1 months ago
A fast simulation approach for inductive effects of VLSI interconnects
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-D...