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INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 8 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 1 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
ECRTS
2007
IEEE
14 years 2 months ago
Predictable Paging in Real-Time Systems: A Compiler Approach
Conventionally, the use of virtual memory in real-time systems has been avoided, the main reason being the difficulties it provides to timing analysis. However, there is a trend ...
Isabelle Puaut, Damien Hardy
DATE
2004
IEEE
175views Hardware» more  DATE 2004»
14 years 8 days ago
Breaking Instance-Independent Symmetries in Exact Graph Coloring
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...
Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Kare...
CC
2006
Springer
124views System Software» more  CC 2006»
14 years 8 days ago
Hybrid Optimizations: Which Optimization Algorithm to Use?
We introduce a new class of compiler heuristics: hybrid optimizations. Hybrid optimizations choose dynamically at compile time which optimization algorithm to apply from a set of d...
John Cavazos, J. Eliot B. Moss, Michael F. P. O'Bo...