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DATE
2006
IEEE
141views Hardware» more  DATE 2006»
14 years 1 months ago
Evaluating coverage of error detection logic for soft errors using formal methods
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
Udo Krautz, Matthias Pflanz, Christian Jacobi 0002...
PST
2008
13 years 9 months ago
Model-Checking for Software Vulnerabilities Detection with Multi-Language Support
In this paper we develop a security verification framework for open source software with a multi-language support. We base our approach on the GCC compiler which is considered as ...
Rachid Hadjidj, Xiaochun Yang, Syrine Tlili, Moura...
JFP
2006
91views more  JFP 2006»
13 years 7 months ago
A reflective functional language for hardware design and theorem proving
This paper introduces reFLect, a functional programming language with reflection features intended for applications in hardware design and verification. The reFLect language is st...
Jim Grundy, Thomas F. Melham, John W. O'Leary
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
14 years 4 days ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
DAC
2005
ACM
14 years 8 months ago
Simulation based deadlock analysis for system level designs
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...