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ECRTS
2010
IEEE
13 years 8 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
APCSAC
2007
IEEE
14 years 1 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
ISHPC
2003
Springer
14 years 19 days ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
ISPASS
2009
IEEE
14 years 2 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 7 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...