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TNN
2010
173views Management» more  TNN 2010»
13 years 3 months ago
Global synchronization for discrete-time stochastic complex networks with randomly occurred nonlinearities and mixed time delays
Abstract--In this paper, the problem of stochastic synchronization analysis is investigated for a new array of coupled discretetime stochastic complex networks with randomly occurr...
Zidong Wang, Yao Wang, Yurong Liu
PDP
2011
IEEE
13 years 14 days ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
EUROPAR
2011
Springer
12 years 8 months ago
A Bit-Compatible Parallelization for ILU(k) Preconditioning
Abstract. ILU(k) is a commonly used preconditioner for iterative linear solvers for sparse, non-symmetric systems. It is often preferred for the sake of its stability. We present T...
Xin Dong 0004, Gene Cooperman
HPCA
2006
IEEE
14 years 9 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 3 months ago
System-level process variability analysis and mitigation for 3D MPSoCs
Abstract—While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D desig...
Siddharth Garg, Diana Marculescu
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