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» Communication Mechanisms for Parallel DSP Systems on a Chip
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IEICET
2010
100views more  IEICET 2010»
13 years 6 months ago
Study of Electromagnetic Noise Coupling in Wireless-LAN Communication System
This paper shows experimental results of packet error rates (PERs) in wireless-LAN mounted printed circuit boards and gives a discussion on a mechanism of electromagnetic noise cou...
Mizuki Iwanami, Hiroshi Fukuda, Manabu Kusumoto, T...
ICDCS
1997
IEEE
14 years 3 days ago
Group Communication Support for Distributed Multimedia and CSCW Systems
The Collaborative Computing Transport Layer (CCTL) is a communication substrate consisting of a suite of multiparty protocols, providing varying service qualities among process gr...
Injong Rhee, Shun Yan Cheung, Phillip W. Hutto, Va...
ICS
2005
Tsinghua U.
14 years 1 months ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda
CODES
2005
IEEE
13 years 9 months ago
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals
We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its...
Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji ...
CORR
2007
Springer
154views Education» more  CORR 2007»
13 years 7 months ago
Application of a design space exploration tool to enhance interleaver generation
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...