362 search results - page 36 / 73 » Communication Mechanisms for Parallel DSP Systems on a Chip |
ICS
2009
Tsinghua U.
14 years 15 days ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
SBCCI
2004
ACM
14 years 1 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Predicting how well applications may run on modern systems is becoming increasingly challenging. It is no longer sufficient to look at number of floating point operations and commu...
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
ISPA
2004
Springer
14 years 1 months ago
2004
Springer
HPL is a parallel Linpack benchmark package widely adopted in massive cluster system performance test. On HPL data layout among processors, a law to determine block size NB theoret...