Reducing test time with processor reuse in network-on-chip based systems

This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time. Categories and Subject Descriptors B.8.1[Performance And Reliability]: Reliability, Testing, and Fault-Tolerance General Terms Algorithms, Reliability. Keywords SoC test, core-based test, software-based test, computeraided test (CAT), network-on-chip, NoC testing.

• Type: Conference
• Year: 2004
• Where: SBCCI
• Authors: Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
• Keywords: On-chip Network, SBCCI 2004, Test Planning Method, Test Time