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» Communication Mechanisms for Parallel DSP Systems on a Chip
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ACSD
2007
IEEE
136views Hardware» more  ACSD 2007»
14 years 2 months ago
Mapping Applications to Tiled Multiprocessor Embedded Systems
Modern multiprocessor embedded systems execute a large number of tasks on shared processors and handle their complex communications on shared communication networks. Traditional m...
Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, K...
CASES
2008
ACM
13 years 10 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ANSS
2007
IEEE
14 years 2 months ago
Performance Analysis of an Optimistic Simulator for CD++
DEVS is a formalism to describe generic dynamic systems in a hierarchical and modular way. We present new techniques for executing DEVS and CellDEVS models in parallel and distrib...
Qi Liu, Gabriel A. Wainer
FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 11 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
HPCA
2008
IEEE
14 years 2 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal