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» Communication Mechanisms for Parallel DSP Systems on a Chip
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IPCCC
2006
IEEE
14 years 1 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
FORTE
2008
13 years 9 months ago
Distributed Semantics and Implementation for Systems with Interaction and Priority
The paper studies a distributed implementation method for the BIP (Behavior, Interaction, Priority) component framework for modeling heterogeneous systems. BIP offers two powerful ...
Ananda Basu, Philippe Bidinger, Marius Bozga, Jose...
CC
2009
Springer
141views System Software» more  CC 2009»
14 years 8 months ago
Compile-Time Analysis and Specialization of Clocks in Concurrent Programs
Abstract. Clocks are a mechanism for providing synchronization barriers in concurrent programming languages. They are usually implemented using primitive communication mechanisms a...
Nalini Vasudevan, Olivier Tardieu, Julian Dolby, S...
MIDDLEWARE
2007
Springer
14 years 2 months ago
A service-oriented middleware for context-aware applications
Context awareness has emerged as an important element in distributed computing. It offers mechanisms that allow applications to be aware of their environment and enable these appl...
Luiz Olavo Bonino da Silva Santos, Remco Poortinga...
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
13 years 6 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...