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CODES
2004
IEEE
14 years 15 days ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
IPPS
1999
IEEE
14 years 1 months ago
The Impact of Memory Hierarchies on Cluster Computing
Using off-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform ...
Xing Du, Xiaodong Zhang
ERSA
2010
115views Hardware» more  ERSA 2010»
13 years 6 months ago
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
Research in communication networks has shown that the Internet architecture is not sufficient for modern communication areas such as the interconnection networks of super computing...
Enno Lübbers, Marco Platzner, Christian Pless...
INFOCOM
2003
IEEE
14 years 2 months ago
MEDF - A Simple Scheduling Algorithm for Two Real-Time Transport Service Classes with Application in the UTRAN
— In this paper, we consider real-time speech traffic, real-time circuit-switched data (CSD) and non-real-time packetswitched data (PSD) in the UMTS Terrestrial Radio Access Net...
Michael Menth, Matthias Schmid, Herbert Heiss, Tho...
IPPS
2007
IEEE
14 years 3 months ago
A Cost-Effective, High Bandwidth Server I/O network Architecture for Cluster Systems
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
Hsing-bung Chen, Gary Grider, Parks Fields