In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
The FlexRay bus is the prospective automotive standard communication system. For the sake of a high flexibility, the protocol includes a static time-triggered and a dynamic event...
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...