Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signicant area overhead and performance degradation...
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...
Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich...