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» Compaction Schemes with Minimum Test Application Time
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MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
ISBI
2004
IEEE
14 years 8 months ago
Statistical Surface-Based Morphometry Using a Non-Parametric Approach
We present a novel method of statistical surface-based morphometry based on the use of non-parametric permutation tests. In order to evaluate morphologicaldifferences of brain str...
Dimitrios Pantazis, Richard M. Leahy, Thomas E. Ni...
HPCA
2009
IEEE
14 years 8 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
SENSYS
2004
ACM
14 years 1 months ago
Synopsis diffusion for robust aggregation in sensor networks
Previous approaches for computing duplicate-sensitive aggregates in sensor networks (e.g., in TAG) have used a tree topology, in order to conserve energy and to avoid double-count...
Suman Nath, Phillip B. Gibbons, Srinivasan Seshan,...
DAC
2005
ACM
14 years 9 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...