Sciweavers

138 search results - page 13 / 28
» Compaction-based test generation using state and fault infor...
Sort
View
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 7 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ATS
2010
IEEE
229views Hardware» more  ATS 2010»
13 years 5 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
27
Voted
TSMC
2011
210views more  TSMC 2011»
13 years 2 months ago
Fault Diagnosis in Discrete-Event Systems: Incomplete Models and Learning
— Most state-based approaches to fault diagnosis of discrete-event systems require a complete and accurate model of the system to be diagnosed. In this paper, we address the prob...
Raymond H. Kwong, David L. Yonge-Mallo
SEFM
2005
IEEE
14 years 1 months ago
Experimental Evaluation of FSM-Based Testing Methods
The development of test cases is an important issue for testing software, communication protocols and other reactive systems. A number of methods are known for the development of ...
Rita Dorofeeva, Nina Yevtushenko, Khaled El-Fakih,...