Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores

Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach ...

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
• Keywords: Computer Architecture, External Scan Pins, Internal Scan Chains, Scan Chains, VLSID 2005