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CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
MVA
2007
210views Computer Vision» more  MVA 2007»
13 years 9 months ago
Represent Image Contents Using Curves and Chain Code
This paper presents a new approach to extracting and representing structural features of images. The approach is based on both a region-based analysis and a contour-based analysis...
Pornchai Mongkolnam, Chakarida Nukoolkit, Thanee D...
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 8 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
14 years 4 days ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
VCIP
2000
13 years 9 months ago
Optimal down-conversion in compressed DCT domain with minimal operations
A new down-conversion scheme in the DCT domain is presented, which can be used in decoders of DCT-compressed images and videos. The down-conversion in the transform domain general...
Myoung-Cheol Shin, In-Cheol Park