Sciweavers

484 search results - page 30 / 97
» Comparative Evaluation of Two Scalable QoS Architectures
Sort
View
ISCAPDCS
2001
13 years 9 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
14 years 1 months ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
HPCA
2005
IEEE
14 years 8 months ago
Characterizing and Comparing Prevailing Simulation Techniques
Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not...
Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag,...
LCN
2003
IEEE
14 years 1 months ago
A User-level Multicast Performance Comparison of Scalable Coherent Interface and Myrinet Interconnects
This paper compares and evaluates the multicast performance of two of the most widely deployed System-Area Networks (SANs), Dolphin’s Scalable Coherent Interface (SCI) and Myric...
Sarp Oral, Alan D. George
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez