484 search results - page 79 / 97 » Comparative Evaluation of Two Scalable QoS Architectures |
SC
2009
ACM
14 years 2 months ago
2009
ACM
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
ARITH
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a n...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— A multi-channel wireless mesh network (MCWMN) consists of a number of stationary wireless routers, where each router is equipped with multiple network interface cards (...
ISPASS
2005
IEEE
14 years 1 months ago
2005
IEEE
Computer architecture research in academia and industry is heavily reliant on simulation studies. While microprocessor companies have the resources to develop highly detailed simu...