A New Family of High.Performance Parallel Decimal Multipliers

This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that uses a novel BCD–4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD–8421 multiplier operand into minimally redundant signed–digit radix–10, radix–4 and radix–5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix–4 and radix–5 recodings allow the reuse of a conventional parallel binary radix–4 multiplier to perform combined binary/decimal multiplications. Evaluation results show that the proposed architectures have interesting area–delay figures compared to conventional Booth radix–4 and radix–8 parallel bi...

• Type: Conference
• Year: 2007
• Where: ARITH
• Authors: Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
• Keywords: Applied Computing, ARITH 2007, Parallel Binary Multipliers, Parallel Decimal Multipliers, Partial Product