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» Comparative Evaluation of Two Scalable QoS Architectures
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DAC
1994
ACM
13 years 12 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
INFOCOM
1992
IEEE
13 years 12 months ago
Design of Virtual Channel Queue in an ATM Broadband Terminal Adaptor
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...
H. Jonathan Chao, Donald E. Smith
CF
2010
ACM
14 years 26 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CAL
2008
13 years 8 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
PET
2010
Springer
13 years 11 months ago
Collaborative, Privacy-Preserving Data Aggregation at Scale
Combining and analyzing data collected at multiple locations is critical for a wide variety of applications, such as detecting and diagnosing malicious attacks or computing an acc...
Benny Applebaum, Haakon Ringberg, Michael J. Freed...