415 search results - page 39 / 83 » Comparative evaluation of memory models for chip multiproces... |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
ICPADS
2006
IEEE
14 years 1 months ago
2006
IEEE
Symmetric Multiprocessors (SMPs), combined with modern interconnection technologies are commonly used to build cost-effective compute clusters. However, contention among processor...
IJCNN
2000
IEEE
14 years 1 days ago
2000
IEEE
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
Task graph scheduling has been found effective in performance prediction and optimization of parallel applications. A number of static scheduling algorithms have been proposed for...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...