415 search results - page 47 / 83 » Comparative evaluation of memory models for chip multiproces... |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
ICCD
1993
IEEE
13 years 11 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
PPOPP
2003
ACM
14 years 27 days ago
2003
ACM
Simultaneous multithreading (SMT) represents a fundamental shift in processor capability. SMT's ability to execute multiple threads simultaneously within a single CPU offers ...
ICS
2010
Tsinghua U.
13 years 10 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...