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DAC
2005
ACM
14 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
APN
1999
Springer
13 years 12 months ago
Parallel Approaches to the Numerical Transient Analysis of Stochastic Reward Nets
Abstract. This paper presents parallel approaches to the complete transient numerical analysis of stochastic reward nets (SRNs) for both shared and distributed-memory machines. Par...
Susann C. Allmaier, David Kreische
HIPS
1997
IEEE
13 years 11 months ago
Complexity and Performance in Parallel Programming Languages
Several parallel programming languages, libraries and environments have been developed to ease the task of writing programs for multiprocessors. Proponents of each approach often ...
Steven P. Vanderwiel, Daphna Nathanson, David J. L...
KDD
2008
ACM
186views Data Mining» more  KDD 2008»
14 years 8 months ago
Cut-and-stitch: efficient parallel learning of linear dynamical systems on smps
Multi-core processors with ever increasing number of cores per chip are becoming prevalent in modern parallel computing. Our goal is to make use of the multi-core as well as multi...
Lei Li, Wenjie Fu, Fan Guo, Todd C. Mowry, Christo...
HPCA
2009
IEEE
14 years 8 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha