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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
DAC
2005
ACM
14 years 8 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
VLDB
2005
ACM
123views Database» more  VLDB 2005»
14 years 7 months ago
Querying XML streams
Efficient querying of XML streams will be one of the fundamental features of next-generation information systems. In this paper we propose the TurboXPath path processor, which acce...
Vanja Josifovski, Marcus Fontoura, Attila Barta
SAC
2010
ACM
14 years 2 months ago
Referrer graph: a low-cost web prediction algorithm
This paper presents the Referrer Graph (RG) web prediction algorithm as a low-cost solution to predict next web user accesses. RG is aimed at being used in a real web system with ...
B. de la Ossa, Ana Pont, Julio Sahuquillo, Jos&eac...
JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi