415 search results - page 8 / 83 » Comparative evaluation of memory models for chip multiproces... |
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
CAL
2010
13 years 5 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and the...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...