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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
SPIN
2000
Springer
13 years 11 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader
EMSOFT
2008
Springer
13 years 9 months ago
Randomized directed testing (REDIRECT) for Simulink/Stateflow models
The Simulink/Stateflow (SL/SF) environment from Mathworks is becoming the de facto standard in industry for model based development of embedded control systems. Many commercial to...
Manoranjan Satpathy, Anand Yeolekar, S. Ramesh
JCC
2007
79views more  JCC 2007»
13 years 7 months ago
Interfacing Q-Chem and CHARMM to perform QM/MM reaction path calculations
Abstract: A hybrid quantum mechanical/molecular mechanical (QM/MM) potential energy function with HartreeFock, density functional theory (DFT), and post-HF (RIMP2, MP2, CCSD) capab...
H. Lee Woodcock III, Milan Hodoscek, Andrew T. B. ...
JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi