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» Comparing Reductions to NP-Complete Sets
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FMCAD
2009
Springer
15 years 10 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
15 years 10 months ago
Simultaneous FU and Register Binding Based on Network Flow Method
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
Jason Cong, Junjuan Xu
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
15 years 10 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
ISCAS
2008
IEEE
139views Hardware» more  ISCAS 2008»
15 years 10 months ago
Missing feature speech recognition in a meeting situation with maximum SNR beamforming
Abstract— Especially for tasks like automatic meeting transcription, it would be useful to automatically recognize speech also while multiple speakers are talking simultaneously....
Dorothea Kolossa, Shoko Araki, Marc Delcroix, Tomo...
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
15 years 10 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu