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ESTIMEDIA
2004
Springer
14 years 23 days ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
RTCSA
2000
IEEE
13 years 11 months ago
Fixed-priority preemptive multiprocessor scheduling: to partition or not to partition
Traditional multiprocessor real-time scheduling partitions a task set and applies uniprocessor scheduling on each processor. By allowing a task to resume on another processor than...
Björn Andersson, Jan Jonsson
CSE
2009
IEEE
13 years 10 months ago
A Comparative Study of Blocking Storage Methods for Sparse Matrices on Multicore Architectures
Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architectur...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ASAP
2009
IEEE
144views Hardware» more  ASAP 2009»
14 years 4 months ago
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study
—In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for ...
Richard Membarth, Philipp Kutzer, Hritam Dutta, Fr...