622 search results - page 33 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
PPOPP
1993
ACM
13 years 11 months ago
1993
ACM
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
TVLSI
2008
13 years 7 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
DATE
2003
IEEE
14 years 21 days ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...