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» Comparing the Optimal Performance of Parallel Architectures
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DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 8 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
HPCA
2009
IEEE
14 years 9 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
APVIS
2007
13 years 10 months ago
Particle-based volume rendering
: In this paper, we apply Particle-based Volume Rendering (PBVR) technique using a current programmable GPU architecture. Recently, the increasing programmability of GPU offers an ...
Naohisa Sakamoto, Jorji Nonaka, Koji Koyamada, Sat...
APLAS
2005
ACM
14 years 2 months ago
Transformation to Dynamic Single Assignment Using a Simple Data Flow Analysis
This paper presents a novel method to construct a dynamic single assignment (DSA) form of array-intensive, pointer-free C programs (or in any other procedural language). A program ...
Peter Vanbroekhoven, Gerda Janssens, Maurice Bruyn...
NSDI
2008
13 years 10 months ago
Swift: A Fast Dynamic Packet Filter
This paper presents Swift, a packet filter for high performance packet capture on commercial off-the-shelf hardware. The key features of Swift include (1) extremely low filter upd...
Zhenyu Wu, Mengjun Xie, Haining Wang