Sciweavers

1461 search results - page 256 / 293
» Comparing the Optimal Performance of Parallel Architectures
Sort
View
HPCA
2006
IEEE
14 years 8 months ago
Store vectors for scalable memory dependence prediction and scheduling
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
Samantika Subramaniam, Gabriel H. Loh
HPDC
2000
IEEE
14 years 27 days ago
Evaluation of Task Assignment Policies for Supercomputing Servers: The Case for Load Unbalancing and Fairness
While the MPP is still the most common architecture in supercomputer centers today, a simpler and cheaper machine configuration is growing increasingly common. This alternative s...
Bianca Schroeder, Mor Harchol-Balter
DAC
2009
ACM
14 years 9 months ago
Non-intrusive dynamic application profiling for multitasked applications
Application profiling ? the process of monitoring an application to determine the frequency of execution within specific regions ? is an essential step within the design process f...
Karthik Shankar, Roman L. Lysecky
EUC
2005
Springer
14 years 2 months ago
An Integrated Scheme for Address Assignment and Service Location in Pervasive Environments
We propose an efficient scheme called CoReS (Configuration and Registration Scheme) that integrates address assignment and service location for ad hoc networks prevalent in pervasi...
Mijeom Kim, Mohan Kumar, Behrooz Shirazi
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
14 years 6 days ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel