1461 search results - page 287 / 293 » Comparing the Optimal Performance of Parallel Architectures |
HPCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
PPAM
2005
Springer
14 years 25 days ago
2005
Springer
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
CGO
2003
IEEE
14 years 19 days ago
2003
IEEE
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
GCC
2003
Springer
14 years 17 days ago
2003
Springer
: In the Grid environment, user can manage and make use of web services, such as uploading or downloading web services. But when user want to download one web services to run it in...