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HPCA
2009
IEEE
14 years 11 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
VLSID
2007
IEEE
146views VLSI» more  VLSID 2007»
14 years 11 months ago
Architecting Microprocessor Components in 3D Design Space
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004,...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 7 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
IPSN
2010
Springer
14 years 5 months ago
High-resolution, low-power time synchronization an oxymoron no more
We present Virtual High-resolution Time (VHT), a powerproportional time-keeping service that offers a baseline power draw of a low-speed clock (e.g. 32 kHz crystal), but provides...
Thomas Schmid, Prabal Dutta, Mani B. Srivastava
AVSS
2009
IEEE
14 years 5 months ago
A 3D Face Model for Pose and Illumination Invariant Face Recognition
Generative 3D face models are a powerful tool in computer vision. They provide pose and illumination invariance by modeling the space of 3D faces and the imaging process. The powe...
Pascal Paysan, Reinhard Knothe, Brian Amberg, Sami...