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CODES
2005
IEEE
13 years 9 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
ICC
2007
IEEE
148views Communications» more  ICC 2007»
14 years 1 months ago
HSDPA Performance in Live Networks
—The first HSDPA (High-Speed Downlink Packet Access) networks have been recently deployed for operational use. We evaluate and compare live HSDPA operational network performance ...
Marko Jurvansuu, Jarmo Prokkola, Mikko Hanski, Pek...
HPCA
2005
IEEE
14 years 7 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
CODES
2008
IEEE
13 years 9 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
PDP
2005
IEEE
14 years 29 days ago
Practicable Layouts for Optimal Circulant Graphs
Circulant graphs have been deeply studied in technical literature. Midimew networks are a class of distancerelated optimal circulant graphs of degree four which have applications ...
Enrique Vallejo, Ramón Beivide, Carmen Mart...