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» Comparison of Hardware and Software Cache Coherence Schemes
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CGO
2005
IEEE
14 years 1 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
EUROCAST
2007
Springer
131views Hardware» more  EUROCAST 2007»
13 years 11 months ago
Efficient Model Checking of Applications with Input/Output
Most non-trivial applications use some form of input/output (I/O), such as network communication. When model checking such an application, a simple state space exploration scheme i...
Cyrille Artho, Boris Zweimüller, Armin Biere,...
ASAP
2009
IEEE
115views Hardware» more  ASAP 2009»
14 years 4 months ago
A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
McEliece scheme represents a code-based public-key cryptosystem. So far, this cryptosystem was not employed because of efficiency questions regarding performance and communicatio...
Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter...
HPCA
1998
IEEE
13 years 11 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
CF
2010
ACM
14 years 19 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...