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» Comparison of the Hardware Performance of the AES Candidates...
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EWSN
2010
Springer
13 years 10 months ago
Virtualising Testbeds to Support Large-Scale Reconfigurable Experimental Facilities
Experimentally driven research for wireless sensor networks is invaluable to provide benchmarking and comparison of new ideas. An increasingly common tool in support of this is a t...
Tobias Baumgartner, Ioannis Chatzigiannakis, Maick...
FCCM
2000
IEEE
131views VLSI» more  FCCM 2000»
13 years 12 months ago
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
Data compression techniques based on Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in data storage and communications. However, since the LZ a...
Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluske...
ASAP
2010
IEEE
171views Hardware» more  ASAP 2010»
13 years 7 months ago
General-purpose FPGA platform for efficient encryption and hashing
Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can b...
Jakub Szefer, Yu-Yuan Chen, Ruby B. Lee
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
13 years 9 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 4 months ago
Single-Pass Redundancy Addition and Removal
Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removab...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska