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» Compilation Techniques for Out-of-Core Parallel Computations
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HPCA
2005
IEEE
14 years 9 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...
CORR
2010
Springer
205views Education» more  CORR 2010»
13 years 8 months ago
Behavioral Simulations in MapReduce
In many scientific domains, researchers are turning to large-scale behavioral simulations to better understand real-world phenomena. While there has been a great deal of work on s...
Guozhang Wang, Marcos Antonio Vaz Salles, Benjamin...
IPPS
1999
IEEE
14 years 26 days ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ICPADS
2007
IEEE
14 years 2 months ago
Loop recreation for thread-level speculation
For some sequential loops, existing techniques that form speculative threads only at their loop boundaries do not adequately expose the speculative parallelism inherent in them. T...
Lin Gao 0002, Lian Li 0002, Jingling Xue, Tin-Fook...
HPCA
2002
IEEE
14 years 9 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...