138 search results - page 19 / 28 » Compiled-code-based simulation with timing verification |
IWPSE
2010
IEEE
13 years 5 months ago
2010
IEEE
We describe our experiences with the process of designing a domain-specific language (DSL) and corresponding model transformations. The simultaneous development of the language an...
QEST
2010
IEEE
13 years 5 months ago
2010
IEEE
Discrete-Time Markov Chains (DTMCs) are a widely-used formalism to model probabilistic systems. On the one hand, available tools like PRISM or MRMC offer efficient model checking a...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
DAC
2003
ACM
14 years 26 days ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...